Jensen Huang's IEEE Medal of Honor: from graphics chips to AI factories

IEEE has named Jensen Huang, founder and CEO of Nvidia, the recipient of its 2026 Medal of Honor, with a $2 million prize. IEEE president and CEO Mary Ellen Randall announced the award on 6 January at the Consumer Electronics Show in Las Vegas. The formal citation is "for leadership in the development of graphics processing units and their application to scientific computing and artificial intelligence."

The wording is narrower than the popular picture of Huang as a business figure. IEEE is crediting a chain of architectural decisions that turned a gaming peripheral into general-purpose parallel hardware. This profile traces that chain and flags where the claims rest on vendor figures rather than independent measurement.

01From chip designer to founder

Huang holds a BSEE from Oregon State University and an MSEE from Stanford. He worked at AMD and LSI Logic before starting Nvidia. At LSI he was director of CoreWare, the company's system-on-a-chip strategy, and he had earlier designed microprocessors at AMD. Nvidia was established in 1993 by Huang, Chris Malachowsky and Curtis Priem. Malachowsky came from Sun Microsystems. Priem had been a graphics chip designer at IBM and Sun. Huang has been president, CEO and a board member since the start.

The problem the founders set out to solve was realistic 3D graphics on personal computers. The first attempt did not work. Nvidia's IPO prospectus reported that NV1 sales fell as Microsoft Direct3D and SGI OpenGL gained adoption. The company stopped selling NV1 in early 1996. It then dropped NV2 development and moved its effort to RIVA 128, which reached the market in 1997 as a 128-bit Direct3D processor. The lesson was to build to the dominant software standards instead of competing with them. That habit shaped the later platform strategy.

02The GPU: moving geometry off the CPU

In 1999 Nvidia shipped the GeForce 256. The company marketed it as the world's first GPU, defined as a single-chip processor with integrated transform, lighting, triangle setup/clipping and rendering engines, able to process at least 10 million polygons per second. Before this, competing 3D accelerators ran those functions on the host CPU. The exception was the standalone transform-and-lighting processor from 3Dlabs.

The numbers are modest by today's standards. According to Jon Peddie Research, the 120 MHz NV10 was built on TSMC's 220 nm process, with 17 million transistors on a 139 mm² die. Four pipelined engines gave a 480 Mpix/s fill rate. The architectural point was the division of labour. Geometry maths (positioning, rotating and lighting vertices) is regular, data-parallel arithmetic. It suits wide hardware better than a general-purpose CPU.

Two caveats are worth keeping. First, the term was not new. Peddie notes that 3Dlabs introduced "GPU" in 1997 for a programmable transform-and-lighting engine, so Nvidia's claim is about popularising and integrating, not coining. Second, IEEE's materials describe a "programmable GPU" in 1999. Technical histories describe the GeForce 256 as adding hardware transform and lighting while increasing the number of fixed pixel pipelines. Programmability in the shader sense came in later generations.

03CUDA: making the pipeline a computer

The step that links graphics to AI is software. Before CUDA, anyone using GPU parallelism for non-graphics work had to recast the problem as graphics operations through OpenGL. Nvidia released CUDA in 2006. The first supporting GPU was the GeForce 8800 GTX, launched in November 2006 on the G80 architecture. That generation introduced unified shaders, so every core could run general computation, and the 8800 GTX had 128 of them. CUDA has three parts: a language that extends C/C++, an API and libraries. Programmers write "kernels", short programs that run on a single execution unit. A large job is split into many small pieces that execute in parallel.

The market response was sceptical at first. Steven Witt's New Yorker account, as relayed by Understanding AI, says Wall Street reacted with dismay. The payoff came six years later. Geoffrey Hinton's students Alex Krizhevsky and Ilya Sutskever trained AlexNet on a pair of GTX 580 GPUs, each with 512 execution units. That let them train a network hundreds of times faster than a CPU would allow. AlexNet depended on CUDA, and the result is widely treated as the start of the deep-learning boom.

Nvidia then began building AI-specific features into the silicon. The Volta-generation V100 (2017) added Tensor Cores, dedicated matrix-multiply units. Per Nvidia's whitepaper, they deliver up to 125 Tensor TFLOPS, up to 12 times the peak throughput of standard FP32 operations on the previous-generation P100. NVLink connected multiple V100s at up to 300 GB/s. The design bet was that deep learning is dominated by matrix multiplication, and that memory bandwidth and chip-to-chip links matter as much as raw arithmetic.

04The "AI factory" scale-up

The same logic now applies at rack scale. Nvidia's GB200 NVL72 connects 72 Blackwell GPUs in a single NVLink domain, with over 1 PB/s of aggregate bandwidth and 30 TB of unified memory. Fifth-generation NVLink gives each GPU 1.8 TB/s of bidirectional throughput, which Nvidia puts at 14 times PCIe Gen5. The aim is to make a rack behave like one accelerator for trillion-parameter models. Nvidia claims 30 times faster real-time LLM inference for such models than earlier systems. That is a vendor figure, and its baseline and workload matter.

The cost is physical. HPE's QuickSpecs for its NVL72 list a nominal rack TDP of 132 kW, with a peak electrical design power around 192 kW. The rack needs a 50 V DC busbar and a liquid manifold. One industry analysis lists facility power, coolant loops, packaging and memory lead times, and CUDA lock-in among the constraints on who can deploy such systems. The "AI factory" label, which Nvidia uses for these installations, is a statement about data-centre engineering as well as chips.

05Impact, recognition and open questions

IEEE's own summary is that the GPU sparked advances across artificial intelligence, computing and medicine. Huang's earlier honours include the Semiconductor Industry Association's Robert N. Noyce Award, the IEEE Founder's Medal and election to the National Academy of Engineering. IEEE also lists the Queen Elizabeth Prize for Engineering among his recent honours. At CES he said he accepted the medal on behalf of all the great employees at Nvidia.

Several things the award does not settle:

• Attribution. The GPU, CUDA and the AI stack were built by large teams, and others had earlier ideas on programmable graphics and GPU computing. The medal honours Huang's leadership, as the citation says, not sole invention.
• Dependence on one platform. CUDA's dominance is a strength for developers and a concentration risk for the industry. Rivals such as AMD's Stream and Microsoft's DirectCompute appeared soon after CUDA but did not displace it.
• Efficiency. Rack-level power of more than 100 kW makes electricity and cooling, not only silicon, the limiting factors for further scaling.
• Evidence. Most headline performance numbers for current products are vendor-published. Independent benchmark data lags the launches.

The medal is notable partly because it goes to someone whose main role is running the company. It also recognises that, in this case, decisions about product architecture, software strategy and the chip supply chain cannot be separated.