Micron Bets on 6F² Cells, Wafer Bonding and High-NA EUV Over 4F² DRAM

Micron has decided not to shrink its DRAM cell by changing its geometry. At a technology webinar on 21 October, Chief Technology and Products Officer Scott DeBoer said the company will keep the 6F² planar layout through several more nodes. It will bring in wafer bonding at the 1ε generation and High-NA EUV lithography after that, and it will hold 3D DRAM until the economics favour it. Samsung, SK hynix and CXMT are pursuing the 4F² alternative, so this is a real divergence in how the industry reaches sub-10 nm-class DRAM.

01Why Micron rejects 4F²

F is the minimum feature size a fab can print, and the cell footprint is quoted in multiples of F². Today's mainstream layout is 6F², a cell 3F long and 2F wide, while 4F² is 2F by 2F. At equal F that is a one-third cut in cell area, or up to 1.5x density in the array. Getting there means standing the transistor up, so source, channel and drain stack vertically rather than lying side by side. The names differ by vendor: Samsung calls its version a vertical channel transistor, SK hynix a vertical gate platform, and CXMT a vertical surrounded gate.

The appeal is clear. Earlier reporting by The Elec said the layout could cut die area by 30% compared with 6F² DRAM. SK hynix's CTO told the VLSI 2025 symposium that the company would apply a 4F² vertical-gate platform and 3D DRAM to nodes at 10 nm level or below.

DeBoer argued that the headline figure overstates what a real chip gets. According to a Stocktwits account of the analyst call, he said capacitor spacing, not cell layout, is the key factor in DRAM density, and he called the claimed 4F² advantage "a bit of a myth." Micron says it can build 4F² at older nodes, but at higher cost and complexity. At the leading edge it sees "fundamental" scaling problems. In the Q&A, per MarketBeat, he said that these problems will ultimately lead to 3D DRAM coming in instead of 4F². The roadmap slide reportedly says Micron is not pursuing 4F² because of increased complexity and cost, after more than two decades of study.

One reason a vertical channel is hard is the floating-body problem. A vertical channel loses the tidy connection to the silicon body, so charge can drift in or out. The array also becomes denser in the dimension where capacitor and contact spacing already limit it. That second point is my reading of DeBoer's capacitor-pitch argument, not a figure Micron has published.

02The planar path: 1δ, then 1ε

Micron's roadmap, as reported:

A mid-20% density gain from 1δ is large for a node that keeps the same cell type. It also means density has to come from tighter pitches and cell-array engineering, not from a new layout. 1δ is built in Boise.

03Wafer bonding at 1ε: known and unknown

The mechanism is simple to state: separately manufactured wafers are joined together. Tom's Hardware reports that Micron has not disclosed how it will implement wafer bonding or what improvement it expects. Any description of Micron's version is therefore inference.

The obvious use is to split the DRAM into two wafers. The memory array is built on one wafer, and the peripheral CMOS (sense amplifiers, drivers, logic) is built on another. The two are then bonded face to face. This is how SK hynix describes its own 4F² demonstration: peripheral circuitry sits beneath the memory cells, and the two are connected by wafer bonding and inter-wafer electrical connections. Samsung reportedly showed a 16 Gb 4F² chip with a vertical channel transistor and wafer-to-wafer hybrid bonding at ISSCC in February 2026.

So wafer bonding is not what separates Micron from its rivals. The cell layout is. Micron keeps the 6F² array and adds a bonded stack. The logic wafer can then be optimised separately. Futurum notes Micron's slides show DRAM CMOS logic performance improving more than 10x from 2020 to 2030, through three high-k metal gate generations into 3D CMOS. Bonding looks like the way to build that logic without the thermal and process constraints of the capacitor flow. That reading is plausible but unconfirmed.

The cost is yield. Bonded wafers need tight alignment, void-free interfaces and good dies on both halves. A defect on either wafer scraps the pair. NAND offers a precedent: Micron's G11 NAND uses wafer-on-wafer bonding and exceeds 400 layers. Its yield will tell us how well the technique carries over to DRAM, but Micron has not said so.

04High-NA EUV and new materials

For the generations after 1ε, Micron plans High-NA EUV for 1ζ and new materials for 1η. Other accounts of the webinar describe both as still in pathfinding, so treat the split as provisional. For the research behind this, Micron is working with Albany NanoTech. DeBoer said Albany's advanced-lithography work is "really driving High-NA EUV roadmap for DRAM." Tom's Hardware cautions that such consortium work is largely pre-competitive IP, not a production commitment.

The trade-off is cost against complexity. High-NA scanners cost far more than current EUV tools and expose a smaller field. In exchange they can print finer pitches in a single exposure and remove multi-patterning steps. For DRAM, where array pitch is the main density lever, that could be worth the cost. It is also the route that keeps the 6F² cell competitive without a layout change. No figures for tool count or insertion layers have been disclosed.

05Density, cost and yield: the real comparison

Micron's argument is about total cost per good bit, not cell area alone. 4F² would shrink the cell, but Micron says it adds complexity and cost and offers limited net density. Rivals counter that vertical structures can cut expensive steps; an SK hynix researcher said vertical-gate designs could halve EUV process cost. That claim comes from earlier reporting and has not been shown in volume production. SK hynix's own 4F² demonstration does not show the yield or manufacturing cost needed for volume production. Samsung's reported schedule is development completion in 2026, quality testing in 2027 and mass production in 2028. That is the test of Micron's bet.

By skipping 4F², Micron concentrates its effort. Futurum argues the choice focuses engineering, capital and supplier co-development on a single architecture change, from planar 6F² directly to 3D DRAM. Futurum judges the architecture call to be right and the 2027 schedule the part still to be proven. The risk is that CXMT or Samsung reaches a working 4F² line first. A second risk is that 3D DRAM arrives later than the planar nodes can sustain. DeBoer described 3D as "a parallel path" that Micron will implement only when it is ideal for cost, complexity and performance.

06Beyond the cell: vertical HBM

The same webinar introduced memory stacked on top of the processor. vHBM and vEIM both depend on hybrid bonding, which gives much denser connections than conventional microbumps. The thermal problem is serious, and Micron is working on heat-spreading structures. One report puts first vHBM products in 2028 and quotes DeBoer on a "very high trade ratio," meaning fewer DRAM dies per wafer. That would add to wafer demand per bit at a time when DeBoer expects supply to stay tight for two years. Micron has not given commercial dates for vHBM, vEIM or custom HBM in its public materials, so the 2028 figure should be taken as directional.

07What remains unproven

Four things are open. Micron has not said how its wafer bonding works or what it gains. The High-NA and new-materials plans are in pathfinding. The 3D DRAM architecture and timing are undisclosed. And no independent data yet shows that 6F² can match a production 4F² chip on cost per bit. The 1δ ramp in the second half of 2027 will give the first hard numbers. The primary source is Micron's presentation and webcast replay, which are on its investor relations site.